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Siemens released the next generation of comprehensive hardware aided verification system

new products seamlessly combine the next generation of virtual platform, hardware simulation and FPGA prototype verification technology, which can significantly shorten the verification cycle

Veloce series products recognized by customers have been further expanded to set a new standard for hardware aided verification system

Siemens digital industrial software recently announced the launch of the next generation of Veloce hardware aided verification system, It can quickly verify highly complex next-generation integrated circuit (IC) designs. The system is the first complete integrated solution in the industry, which integrates the first-class virtual platform, hardware simulation and FPGA prototype verification technology, and lays a solid foundation for the application of the new method of hardware assisted verification

new products in Veloce hardware assisted verification system include:

Veloce hycon (hybridconfigurable) for virtual platform/software activation verification. Veloce hycon provides an innovative technology that can help customers design and deploy complex hybrid simulation systems for their next-generation SOC (system on chip)

veloce strato+ upgraded version of Veloce Strato hardware simulator. With its leading ability to scale to 15billion gate circuits, Veloce strato+ not only has the highest total processing capacity in the industry, but also can combine it with the fastest collaborative model bandwidth and visibility speed to maximize its function

veloce primo enterprise FPGA prototype verification system. This is a self-developed enterprise prototype design solution, which combines industry-leading performance with rapid prototype start-up

veloce profpga desktop FPGA prototype verification system. Veloce profpga series products adopt a modular capacity scheme, which can provide corresponding scalability according to different capacity requirements

the highly integrated system released this time sets a new standard for the development direction of hardware assisted verification methods. The system can simplify and optimize the verification cycle, and reduce the verification cost, so as to raise the intelligent digitization of hardware, software and system verification to a higher level

this method of seamlessly managing the validation cycle emphasizes running market-specific actual workloads, frameworks, and benchmarks in the early stages of the validation cycle for power consumption and performance analysis. In this way, customers can build a virtual SOC model and integrate it at the initial stage of development, and run the actual firmware and software on Veloce strato+, so as to have an in-depth understanding of the lowest level of hardware. Then, the customer can transfer the same design to Veloce primo and run it at a speed closer to the actual system, so as to verify the software/hardware interface and execute the application level software to be repaired before restarting. In order to make this method as efficient as possible, Veloce strato+ and Veloce primo use the same RTL, the same virtual verification environment, the same trader and model, which can reuse the verification materials, environment and test content to the greatest extent, thus providing the necessary basis for the implementation of a seamless method

ravi Subramanian, senior vice president and general manager of Siemens EDA, said: as we enter the new semiconductor boom cycle, software centered SoC design has brought fundamental changes to the functional verification system to meet higher requirements. The next generation Veloce system came into being, which is the direct result of Siemens' continuous investment and focus on customer needs. Now we can provide customers with a complete integrated system and formulate a clear technical roadmap for the next decade. The release of this product marks that we are establishing new system standards to meet the verification requirements of different industries such as computing, storage, artificial intelligence/machine learning, 5g, networking and automotive

the key to the expansion of Veloce hardware assisted verification system is the innovation in chip, system and software design, which makes Veloce strato+ realize the capacity roadmap released when the Veloce Strato platform was launched in 2017. Due to the innovative design and manufacturing of the new proprietary 2.5D chip crystal 3+, the system capacity is 1.5 times higher than the previous Veloce Strato system. This innovation, which uses the first batch of new materials, is the beneficiary of insurance, enabling Veloce strato+ to occupy the leading position in the simulation market with a capacity of 15billion gates, which is the highest effective capacity in the market today, and has been adopted by many Veloce strato+ customers

amd enterprise academician and method architect Alex Starr said: AMD has adopted Veloce simulation platform in chip verification and validation solutions. The high-performance design we developed requires scalable, reliable and innovative simulation solutions. We are very happy to cooperate with Siemens to take the lead in deploying high-capacity Veloce strato+ system in AMD. In addition, we are also very pleased to see that our second and third generation AMD epyc processors can be used on Veloce Strato and Veloce strato+ platforms. The high performance of these two processor families can bring higher design productivity to Veloce ecosystem and customers including AMD

veloce Strato system also adds AMD epyc 7003 series as qualified processors. These new processors can be used as the running host and collaborative model host of Veloce Strato system

veloce primo and Veloce profpga are the most powerful and general FPGA prototype solutions in the industry. The enterprise FPGA prototype system Veloce primo can provide excellent performance, and the capacity can be expanded to 320 FPGAs. In terms of software workload, design model and front-end compilation technology, it adopts a working model consistent with Veloce Strato. This basic consistency between hardware simulation and prototype verification will help to reduce the cost of verification. By using the right tools to complement simulation and prototype verification, the best results can be obtained in the shortest cycle. Veloce primo also supports virtual (simulation offload) and ice (in circuit emulation) usage models, which can maintain accurate clock ratios in both modes and achieve maximum performance

Hanneke krekels, senior director of Xilinx core vertical market, said: we are glad to see Siemens launch Veloce primo for FPGA prototype verification market. Xilinx has established a long-term customer and partnership with Siemens. Our industry-leading virtex ultrascale+ vu19p latest equipment can help Siemens achieve excellent scalability and capacity in this new product portfolio

Siemens also signed an OEM agreement with pro design, making Veloce profpga provide a world-class mature desktop platform for Veloce hardware assisted verification system. Veloce profpga series products adopt a modular capacity scheme, which can adopt Intel Stratix 10 GX 10m, virtex ultrascal and the influence of some factors on part wear. E+ vu19p high-end FPGA can meet the various capacity expansion requirements from 40million gates to 800million gates to enhance the cultivation of new material market